1. Field of the Invention
This invention relates to a method for manufacturing MOS semiconductor devices, and more particularly to a self-alignment process for forming contact electrodes.
2. Description of the Related Art
Recently, semiconductor elements have been made smaller in size. However, the alignment tolerance required when a self-alignment process is effected for forming MOS transistors makes it difficult to attain the fine semiconductor elements. It is necessary to provide such an alignment tolerance when the limited processing precision and mask alignment precision of an exposure device are taken into consideration.
FIG. 1 shows the cross section of a MOS transistor to illustrate the alignment tolerance. As is clearly shown in FIG. 1, distance L1 is provided between gate electrode 1 and contact holes 4 and 5 formed in the source and drain regions of the MOS transistor and distance L2 is provided between contact holes 4 and 5 and element isolation region 6 as the alignment tolerance.
If contact holes 4 and 5 are formed without providing the alignment tolerance and when mask displacement occurs, then gate electrode 1 may be short-circuited with contact electrodes 7 and 8 which are formed in contact holes 4 and 5 and contact holes 4 and 5 may be formed on element isolation region 6 to cause the contact electrodes to be electrically connected with the substrate.